OMNIBUS is the name given to the backplane connectors on PDP-8/e computers. It is also used on a few other PDP-8 computers (8/f, 8/m, 8/a and perhaps others).
After about a year of procrastinating, using KiCAd I have finally (April 2018) got around to laying out an OMNIBUS “sea of holes” prototyping board that will take 2 x ATF1508 CPLDs.
The key features of this board are:
- The geometry is a standard DEC “quad-height, standard-length” board. This means it has 4 OMNIBUS edge-connector fingers, but only extends half-way from the backplane. In DEC’s terminology, a board that extends all the way from the backplane to the lid is known as “extended-length”.
- Both CPLDs are already wired for GND and +5V.
- There is one on-board DIP-8 5V TTL oscillator module. This is wired to both CPLDs.
- The top edge of the board has footprints for 3 x 40-pin right-angle headers, and 2 banks of 8-way piano-style dipswitches (and associated pull-up resistors).
This prototyping board is intended to be mounted on an “extended-length” extension card, so that it protrudes clear of the other PCBs.
This is the source document that I have used for the physical dimensions of the PCB -> OMNIBUS Dimensions.
Some of the board dimensions were difficult to interpret in that document, as it wasn’t always clear where the dimension arrowheads were pointing. So please excuse any mistakes that I may have made.
Note that the dip switches and headers along the top edge infringe the area that DEC intended to be free of components. I can’t see any real problem with this for a standard-height prototype board. It could be a problem with an extended-height board, as the vertical clearance available for components (0.375 inch) would be infringed by the thickness of the handles on the adjacent PCB.
KiCad parameters used
These are the settings that were used in KiCad PCB (in inches or mils):
- Grid origin: 2.517, 1.05
- Grid: 25 mils
- Line thickness for component outlines: 12 mils
- Location of OMNIBUS connector: 13.000, 9.500
- Hole sizes (most components, vias and sea-of-holes): 60 mils with 36 mil hole
- Hole size for PLCC sockets: 55 mils with 32 mil hole
- Track widths: 15, 20, 25, 70, 200 mils
- Text size for component designators and most labels: 50 high, 50 wide, 8 thick
- Text size for PLCC pins on bottom layer: 30 high, 30 wide, 4 thick
- Minimum track-to-pad spacing: 10 mils (I set it for 9 mils, to avoid false errors)
Downloads
Here are all the relevant design files (for the V1.0 design, dated 18 April 2018):
Recent developments
I also have a more generic Omnibus prototyping board that is ready to get made. See picture on the right here.
Revision history
18 April 2018: Posted initial version