This page has my rough notes about various CPLD and FPGA development boards.
Terasic DE10-Lite FPGA board
The DE10-Lite is fitted with an Altera MAX10 FPGA.
The actual FPGA is: 10M50DAF484C6GES
The software suite that I am using to program it is “Intel Quastus Prime 17.1”.
3.3V-to 5V Interfacing
Analog Devices MT-098 Tutorial
Options for doing the level translation include:
- TXB0108
- SN74LVC245A
- BSS138
OMNIBUS Interfacing
Steve Lafferty’s webpage on the OMNIBUS 32K RAM board has extensive notes regarding the ICs used by DEC.
Eric Smith’s webpage on DEC bus interface chips also has lots of useful information.
The key points are:
- The standard receiver was a “DEC 380” also known as an “SP380”. These are still available on eBay.
- The standrad Transmitter was a “DEC 8881”. It is an open-collector driver. Output voltage is typically 0.4-0.6 (maximum 0.8V) when sinking 50mA. It is commonly thought that the 8881 is a DEC-rebranded 7439.
In 2014, Vince put together a 32K RAM board based on Steve’s design. Vince’s webpage is here, and the PDF of the schematic is here.
The “omniusb” prject uses 7438’s to drive the bus. Its an open-collector 4 x NAND gate, with a maximum output voltage of 0.4V when sinking a 48mA load. The datasheet for the 7438 is here.
A 7406 or 7407 could probably also be used to drive the bus 9they both have open-collector outputs). However, they can only sink 40mAwith an output voltage of 0.7V. The 7406 datasheet is here.
Resources
NandLand’s Verilog Totorials and Examples
Youtube video: How to create a Quartus Prime project from scratch and assign pins for the DE10-Lite
Nandland’s page on tri-state outputs in Verilog.
Verilog on the ATF1508
It has been mentioned to me that an old version of Altera’s Quartus II software can be used to develop in Verilog or VHDL to target the Atmel ATF1508AS device.
The process is documented in Atmel’s Application Note 0916.
The main steps are:
- Download and install a version of Quartus II that supported the MAX7000 series (ie version 13.0 SP 1). Make sure you tick the box to download the MAX7000 device support.
- In Quartus, target the MAX7000 part that has 128 macrocells. I selected EPM7128SLC84-15. Do the pin assignments in Qartus, as if you were intended to use the Altera device.
- After compiling your design in Quartus, use Atmel’s “pof2jed” Windows utility to convert the .pof file (generated by Quartus) to a .jed file. Note it is important to set JTAG Mode to “On” (rather than “Auto”) and to rick “Enable TDI_PULLUP” and “Enable TMS_PULLUP”, to make sure the JTAG port remains enabled after the programmer operation is completed (so the device can later be re-programmed via the JTAG interface).
- Program the JEDEC file into the ATF1508AS via a JTAG programmer. Note that you won’t be able to use the Quartus II Programmer software (in comination with a USB Blaster) for this task. The Quartus II Programmer will see the Atmel ATF1508AS in the JTAG chain, but won’t allow a .JED file to be downloaded to it. Instead, you need to use the Atmel ATMISP7 programmer application (in Windows) in combination with the Atmel xxxx1150 JTAG programmer.
Some additional information about the Atmel JTAG interface (and a screenshot showing the pof2jed application) is included in Atmel’s ATF15xx In-System Programming User Guide.
Further information about Atmel’s ATMISP software is available here -> http://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/software/atmisp.
Note there is also some more information about the JTAG interface (including recommended pull-up and pull-down resistors) in Altera’s Application Note 95.
Setting up a new project in Quartus Prime 17.1
Here are the key steps:
- Using Windows Explorer, create a new directory somewhere to hold your project files.
- From within Quartus, select File -> New Project Wizard
- At the “Directory, Name, Top-Level Entity” screen: Select the directory that you just created, and give the project a name. Do not use a hyphen in the project name.
- On the next screen, select “Empty project” (rather than Project template).
- On the next screen (“Add Files”), just click “Next”
- On the next screen (“Family, Device & Board Settings”), select this device -> 10M50DAF484C6GES
- On the next screen (“EDA Tool Settings”), for “Simulation” select “ModelSim-Altera”
You should now be back in the main screen of Quartus. In the “Project Navigator” panel in the top-left corner, you should see a line listing your device, and a line below it with the name of your top-level file (which doesn’t yet exist).
Click on the left-most icon on the toolbar (“New”). In the listbox that appears, select “Verilog HDL File” and click OK. Your new blank file appears in the editor window. Click on the “Save” icon on the toolbar.
Type in your Verilog file, and save it.
The next task is to map your Verilog I/O signals to the pins on the FPGA.
Select Assignments -> Pin Planner
input i_clock;
input i_enable;
input i_switch_1;
input i_switch_2;
output o_led_drive;
EP2C5 Cyclone II Mini Board
This is a cheap FPGA development board that can be found (in April 2018) on eBay for around A$20.
It comes with no documentation. You can download the schematic and PCB layout from here.
A simple “Getting Started” guide is available here -> http://www.leonheller.com/FPGA/FPGA.html
The next 3 paragraphs largely come from Leon Heller’s web-page. So please look there for a fuller description.
This board is fitted with an Altera EP2C5T144C8 Cyclone II FPGA. It has 4068 logic elements, 26 x 4k RAM blocks giving a total of 119,898 bits, 13 multipliers, two PLLs, and 89 I/Os. Maximum clock frequency is 300 MHz.
Designs are developed for this board using Quartus II 11.0 Web Edition software from the Altera web site.
The board is fitted with a EPCS4 flash configuration memory chip, and a 50 MHz oscillator. Most of the I/Os are brought out to four 2×14 way headers, which may be connected to external circuitry via wire jumpers, or PCBs fitted with matching sockets. Three LEDs are connected to pins 3, 7 and 9, and a push-button is connected to pin 144.
My stock of MAX7000 CPLDs
To be programmable over JTAG, the device needs to be the “s” version (eg EPM7128S).
Here’s the list of MAX7000’s that I’ve acquired to date:
- 5 x EPM7128SLC84-15 purchased on eBay from China on 11/04/2018. Total price US$6.40 for the lot, including postage. They arrived “JTAG locked”. I shipped them to Bruce in the U.S. and he unlocked them (on a Data I/O 2900?). He kept 3 and returned 2 to me. I’m using 2 of these currently (7/2024), one in the Omnibus high-speed serial board, and the other in the Omnibus 32K/bootloader board.
- 4 x EPN7128SLC84-15’s were purchased for US$3.05 each (plus small postage cost) from utsource on 15/05/2018 (along with 2 x ATF1508’s). As of 07/2024, I’m not sure what happened to these.
- 20 x EPM7128SLC84-15. Purchased on eBay for US$25.60 (for QTY 20) plus US$2.56 postage on 15/03/2020. Order quantity was 20, but 25 were delivered. They looked to be new (were still in individual plastic carriers). I tested one of them in July 2024 and it programmed just fine over JTAG interface.
- 5 x EPM7128SLC84-15N purchased on Aliexpress for A$25.12 on 09/07/2024. These all turned out to be OK, but were difficult to program initially. I suspect they had significant oxidisation on the leads. They were JTAG locked, but with perserverance I was about to unlock them on the Altera LP6. The LP6 kept reporting “pin continuity” errors (and so wouldn’t start a programming cycle), but with multiple attempts at cleaning and sanding the legs, each eventually was able to be programmed (and hence JTAG unlocked) on the LP6. Subsequently, each was able to be JTAG programmed using the Altera USB Blaster. However, again, this took several attempts.
Quartus II for MAX7000 Series
The current version of Quartus as at May 2018 (Quartus Prime 17.1) does not support the old MAX7000 series, such as the EPM7128SLC84-15.
So I downloaded and installed “Quartus II Web Edition” version 13.0sp1. You can choose between 3 download options: Combined Files, Individual Files or DVD Files. I chose the “Individual Files” option, but later came back and downloaded the “DVD FIles”.
To download the Quartus II software you must be logged into your “myAltera” account. Otherwise you will be presented with a “Sign In” screen when you try to commence the download.
You will be given a choice between two Download Methods: “Akamai DLM3 Download Manager” or “Direct Download”. If you choose the former, you will be prompted to download and install the Akamai download software, before the download of Altera software proceeds.
Before commencing the “Individual Files” download operation, I selected the following components:
- Quartus II Software
- ModelSim-Altera Starter Edition
- Arria II
- Cyclone II/III/IV
- Cyclone V
- MAX II, MAX IV, MAX 3000, MAX 7000
- Quartus II Programmer and SignalTap II
- Quartus II Help
This resulted in a download of 4.07GB.
During the installation process, it reported that the required disk space was 10622MB.
This software installed fine on Windows 10 on my Surface Pro 4. However, the Quartus II Programmer was unable to see any devices on the JTAG chain (though the application could see the USB Blaster), and it caused Windows to crash every 10 minutes or so.
This problem is documented by Altera on this web page. I downloaded the updated USB Blaster drivers that are mentioned on that page. They are available from here -> https://www.altera.com/content/dam/altera-www/global/en_US/kdb/rd05162012_935/usb-blaster.zip.
I deleted the old drivers without any trouble. But when I tried to install the “new” (November 2011) drivers, Windows 10 reported a “bad hash” (or similar message) and refused to install them. It turns out this is because the drivers are unsigned. You need to go through a special shutdown/restart process to allow the unsigned drivers to be loaded. The process is shown on this Youtube video. After following that process, I installed the new drivers successfully. The Quartus II Programmer was now able to see the JTAG chain, and the computer-crashing problem ceased.
Update July 2024
I decided to install Quartus II 13.0 SP1 on a Pentium 3 machine (my Super P3-500 tower). Basic specs of that machine are:
- Pentium III, 500 Mhz
- Motherboard: XXX
- 32GB DOM SSD IDE hard drive
- 384MB PC100 168-pin SDRAM
- 2 x USB 1.0 ports
- Video card:
I first installed Windows XP SP3 using the VL (Volume Licensing) software and CDKEY downloaded from archive.org. This version appears not to need to “phone home” to Microsoft to validate the CDKEY (whereas the SP2 VL does need to do that validation within the first 30 days).
I then installed Quartus II 13.0 SP1, the Help files, and MAXII family devices (Files “QuartusSetupWeb-13.0.1.232.exe”, “QuartusHelpSetup-13.0.1.232.exe” and “max_web-13.0.1.232.qdz”). By having these 3 files in the same temporary directory (or on a USB stick), Quartus II will give you the option to install the main software, the help files, and the devices at the same time. The install of Quartus II went smoothly (but took approximately 2.5 hours from a USB stick on a USB 1.0 port), but it would not run. It reports the following error: “The application failed to initialize properly (0xc0150002). Click on OK to terminate the application”. It turns out this is because the “Microsoft Visual C++ Redistributable” has not been installed. I found and installed the 2005 version of the redistributable. It installed fine, but the error persisted. So I deleted that and installed the 2008 redistributable (filename is “vcredist_x86 (2008).exe”. Finally, success! Quartus II 13.0 SP1 now runs fine on the PIII-500 machine.
I then investigated what programmers are supported by this setup. ByteBlaster (parallel port cable) is supported without any need for special drivers. USB Blaster is supported, but you first need to install [this driver] through Device Manager. And unfortunately the Altera LP6 ISA card is not found or supported by this version of Quartus II (even if it is plugged into the ISA slot).
Miscellaneous Resources
Youtube Video by Greg Crist: Getting started with Verilog Testbenches
Setting up Simulation in Quartus II
There are several ways this can be done.
For example, you can write code in Quartus II that will define the output timespan and resolution, and provide the simulation inputs.
I prefer the ‘Univeristy Program VWF” graphical approach. This involves using File -> New to create a graphical display of inputs and outputs, and using Edit -> Value -> Overwrite Clock to stimulate the inputs. This technique is described in this YouTube video -> Creating a Waveform Simulation for Altera FPGAs (Quartus version 13 and newer) (Sec 4-4B )
To make this work in Quartus II 13.0sp1, I had to make a change that is approximately described in this Altera webpage. The steps are as follows:
- Locate the file
\modelsim_ase\modelsim.ini and turn off “read-only” mode in file properties. - Edit that file. In the “Library” section, add the following line: “max7000s_ver = C:\altera\13.0sp1\modelsim_ase\altera\verilog\max”
Testing of 32K CPLD Board – June 2018
.DIR DHK???.* DHKAAB.DG 15 DHKAFA.DG 14 DHKLDA.DG 15 DHKABA.DG 4 DHKAGA.DG 11 DHKMAD.DG 17 DHKACA.DG 5 DHKEBB.DG 17 DHKMCC.DG 14 DHKADA.DG 4 DHKECA.DG 12 DHKPAB.DG 3 12 Files in 131 Blocks - 1 Free blocks .R DHKMAD.DG PDP-8E EXT MEM DATA & CHKBD KM8 SELECTED FOR TESTING SELECT FIELD PARAMETERS SR=0007 SELECT TEST PARAMETERS SR=0007 03 FIELDS IN THIS SYSTEM FIELDS SEL'D ARE 0:210 PROG WILL RELOCATE END OF PASS 0001 END OF PASS 0002 END OF PASS 0003 END OF PASS 0004 END OF PASS 0005^C . [Halted the system, installed the 32K RAM board with only Field 3 enabled] .R DHKMAD.DG PDP-8E EXT MEM DATA & CHKBD KM8 SELECTED FOR TESTING SELECT FIELD PARAMETERS SR=0007 SELECT TEST PARAMETERS SR=0007 04 FIELDS IN THIS SYSTEM FIELDS SEL'D ARE 0:3210 PROG WILL RELOCATE PR LOC FAIL ADR GOOD BAD PATTERN 001462 030000 0000 4000 ALL 1 - 1C 001462 030000 7777 3777 ALL 1 - 2C 001462 030002 0000 4000 ALL 1 - 1C 001462 030002 7777 1777 ALL 1 - 2C 001462 030004 0000 6000 ALL 1 - 1C 001462 030010 0000 6000 ALL 1 - 1C 001462 030020 0000 4000 ALL 1 - 1C 001462 030020 7777 3777 ALL 1 - 2C 001462 030021 0000 4000 ALL 1 - 1C 001462 030021 7777 3777 ALL 1 - 2C 001462 030022 0000 6000 ALL 1 - 1C 001462 030022 7777 3777 ALL 1 - 2C 001462 030023 0000 4000 ALL 1 - 1C 001462 030023 7777 3777 ALL 1 - 2C 001462 030024 0000 4000 ALL 1 - 1C 001462 030024 7777 3777 ALL 1 - 2C 001462 030025 0000 4000 ALL 1 - 1C 001462 030025 7777 3777 ALL 1 - 2C 001462 030026 0000 4000 ALL 1 - 1C 001462 030026 7777 3777 ALL 1 - 2C 001462 030027 0000 4000 ALL 1 - 1C 001462 030027 7777 1777 ALL 1 - 2C 001462 030030 0000 4000 ALL 1 - 1C 001462 030030 7777 3777 ALL 1 - 2C 001462 030031 0000 4000 ALL 1 - 1C 001462 030031 7777 3777 ALL 1 - 2C 001462 030032 0000 6000 ALL 1 - 1C 001462 030032 7777 1777 ALL 1 - 2C 001462 030033 0000 4000 ALL 1 - 1C 001462 030033 7777 3777 ALL 1 - 2C 001462 030034 0000 4000 ALL 1 - 1C 001462 030034 7777 1777 ALL 1 - 2C 001462 030035 0000 4000 ALL 1 - 1C 001^C .
Next set is with the OE equation simplified
. .R DHKMAD.DG PDP-8E EXT MEM DATA & CHKBD KM8 SELECTED FOR TESTING SELECT FIELD PARAMETERS SR=0007 SELECT TEST PARAMETERS SR=0007 04 FIELDS IN THIS SYSTEM FIELDS SEL'D ARE 0:3210 PROG WILL RELOCATE PR LOC FAIL ADR GOOD BAD PATTERN 001462 030406 0000 0050 ALL 1 - 1C 001462 030446 0000 0040 ALL 1 - 1C 001462 030506 0000 0050 ALL 1 - 1C 001462 030550 0000 0010 ALL 1 - 1C 001462 030626 0000 0010 ALL 1 - 1C 001462 030632 0000 0010 ALL 1 - 1C 001462 030646 0000 0050 ALL 1 - 1C 001462 030650 0000 0050 ALL 1 - 1C 001462 031400 0000 0050 ALL 1 - 1C 001462 031401 0000 0040 ALL 1 - 1C 001462 031403 7777 7737 ALL 1 - 2C 001462 031405 0000 0040 ALL 1 - 1C 001462 031407 0000 0040 ALL 1 - 1C 001462 031410 0000 0050 ALL 1 - 1C 001462 031411 0000 0040 ALL 1 - 1C 001462 031412 7777 7727 ALL 1 - 2C 001462 031414 7777 7727 ALL 1 - 2C 001462 031415 7777 7737 ALL 1 - 2C 001462 031417 0000 0040 ALL 1 - 1C 001462 031432 0000 0010 ALL 1 - 1C 001462 031436 0000 0010 ALL 1 - 1C 001462 031441 0000 0040 ALL 1 - 1C 001462 031443 0000 0040 ALL 1 - 1C 001462 031445 0000 0040 ALL 1 - 1C 001462 031447 0000 0040 ALL 1 - 1C 001462 031451 0000 0040 ALL 1 - 1C 001462 031453 0000 0040 ALL 1 - 1C 001462 031453 7777 7737 ALL 1 - 2C 001462 031455 7777 7737 ALL 1 - 2C 001462 031456 0000 0010 ALL 1 - 1C 001462 031472 7777 7767 ALL 1 - 2C 001462 031476 7777 7767 ALL 1 - 2C 001462 031501 0000 0040 ALL 1 - 1C 001462 031503 7777 7737 ALL 1 - 2C 001462 031505 0000 0040 ALL 1 - 1C 001462 031507 0000 0040 ALL 1 - 1C 001462 031510 0000 0050 ALL 1 - 1C 001462 031512 0000 0050 ALL 1 - 1C 001462 031513 0000 0040 ALL 1 - 1C 001462 031515 0000 0040 ALL 1 - 1C 001462 031517 0000 0040 ALL 1 - 1C 001462 031541 0000 0040 ALL 1 - 1C 001462 031543 0000 0040 ALL 1 - 1C 001462 031547 0000 0040 ALL 1 - 1C 001462 031550 0000 6001 ALL 1 - 1C 001462 031552 0000 0050 ALL 1 - 1C 001462 031556 0000 0050 ALL 1 - 1C 001462 031572 0000 0010 ALL 1 - 1C 001462 031576 0000 0010 ALL 1 - 1C 001462 031601 0000 0040 ALL 1 - 1C 001462 031603 0000 0040 ALL 1 - 1C 001462 031605 0000 0040 ALL 1 - 1C 001462 031607 0000 0040 ALL 1 - 1C 001462 031610 0000 0050 ALL 1 - 1C 001462 031611 0000 0040 ALL 1 - 1C 001462 031612 0000 0050 ALL 1 - 1C 001462 031613 0000 0040 ALL 1 - 1C 001462^C .
Next block shows what happens now the 74LS14 has been added:
.NOW FIELDS 3,4,5,6,7 ARE SWITCHED TO ACTIVE NOW? .R DHKMAD.DG PDP-8E EXT MEM DATA & CHKBD KM8 SELECTED FOR TESTING SELECT FIELD PARAMETERS SR=0007 SELECT TEST PARAMETERS SR=0007 10 FIELDS IN THIS SYSTEM FIELDS SEL'D ARE 0:76543210 PROG WILL RELOCATE END OF PASS 0001 15 END OF PASS 0002 END OF PASS 0003 15 END OF PASS 0004 END OF PASS 0005 15 END OF PASS 0006 END OF PASS 0007 15 END OF PASS 0010 END OF PASS 0011 15 END OF PASS 0012 END OF PASS 0013 15 END OF PASS 0014 END OF PASS 0015 15 END OF PASS 0016 END OF PASS 0017 15 END OF PASS 0020 END OF PASS 0021 15 END OF PASS 0022 END OF PASS 0023 15 END OF PASS 0024 END OF PASS 0025 15 END OF PASS 0026 END OF PASS 0027 15 END OF PASS 0030 END OF PASS 0031 15 END OF PASS 0032 15 END OF PASS 0033 END OF PASS 0034 15 END OF PASS 0035 END OF PASS 0036 15 END OF PASS 0037 END OF PASS 0040 15 END OF PASS 0041 END OF PASS 0042 15 END OF PASS 0043 END OF PASS 0044 15 END OF PASS 0045 END OF PASS 0046 15 END OF PASS 0047 END OF PASS 0050 15 END OF PASS 0051 END OF PASS 0052 15 END OF PASS 0053 END OF PASS 0054 15 END OF PASS 0055 END OF PASS 0056 15 END OF PASS 0057 END OF PASS 0060 15 END OF PASS 0061 END OF PASS 0062 15 END OF PASS 0063 END OF PASS 0064 15 END OF PASS 0065 15 END OF PASS 0066 END OF PASS 0067 15 END OF PASS 0070 END OF PASS 0071 15 END OF PASS 0072 END OF PASS 0073 15^C . .BOARD NOW RELOACTED TO CENTRE OF CHASSIS (WAS JUST IN FRONT OF CORE) BOARD? . .R DHKMAD.DG PDP-8E EXT MEM DATA & CHKBD KM8 SELECTED FOR TESTING SELECT FIELD PARAMETERS SR=0007 SELECT TEST PARAMETERS SR=0007 10 FIELDS IN THIS SYSTEM FIELDS SEL'D ARE 0:76543210 PROG WILL RELOCATE END OF PASS 0001 15 END OF PASS 0002 END OF PASS 0003 15 END OF PASS 0004 END OF PASS 0005 15
On 09.07.2018, I finally worked out how to enter the SR values into DHKMAD.DG:
.R DHKMAD.DG PDP-8E EXT MEM DATA & CHKBD KM8 SELECTED FOR TESTING SELECT FIELD PARAMETERS SR=0007 0307 SELECT TEST PARAMETERS SR=0307 0400 10 FIELDS IN THIS SYSTEM FIELDS SEL'D ARE 0:76543 NO RELOCATION, PROG IN FIELD 0 15 15
09.07.2018: Here’s what I get if I replace the 74LS14 with a 74LS04:
.R DHKMAD.DG PDP-8E EXT MEM DATA & CHKBD KM8 SELECTED FOR TESTING SELECT FIELD PARAMETERS SR=0007 0307 SELECT TEST PARAMETERS SR=0307 0400 10 FIELDS IN THIS SYSTEM FIELDS SEL'D ARE 0:76543 NO RELOCATION, PROG IN FIELD 0 PR LOC FAIL ADR GOOD BAD PATTERN 001462 030376 0000 0400 ALL 1 - 1C 001462 031023 0000 4440 ALL 1 - 1C 001462 031035 0000 0440 ALL 1 - 1C 001462 031037 7777 7337 ALL 1 - 2C 001462 031065 0000 0400 ALL 1 - 1C 001462 031071 7777 7377 ALL 1 - 2C 001462 031074 0000 0400 ALL 1 - 1C 001462 031171 0000 4600 ALL 1 - 1C 001462 031174 0000 4600 ALL 1 - 1C 001462 031175 7777 7177 ALL 1 - 2C 001462 032574 0000 0600 ALL 1 - 1C 001462 033165 0000 0400 ALL 1 - 1C 001462 033171 0000 0600 ALL 1 - 1C 001462 033371 0000 0600 ALL 1 - 1C 001462 040204 7777 7357 ALL 1 - 2C 001462 040422 7777 7337 ALL 1 - 2C 001462 041075 0000 0420 ALL 1 - 1C 001462 042005 7777 7357 ALL 1 - 2C 001462 042045 0000 0420 ALL 1 - 1C 001462 042144 7777 7377 ALL 1 - 2C 001462 042155 7777 7357 ALL 1 - 2C 001462 042304 7777 7377 ALL 1 - 2C 001462 042411 7777 3777 ALL 1 - 2C 001462 042607 0000 4400 ALL 1 - 1C 001462 042611 0000 4000 ALL 1 - 1C 001462 042617 7777 3377 ALL 1 - 2C 001462 044004 7777 7377 ALL 1 - 2C 001462 044050 7777 7377 ALL 1 - 2C 001462 044151 7777 7377 ALL 1 - 2C 001462 044172 7777 7377 ALL 1 - 2C 001462 044213 7777 7377 ALL 1 - 2C 001462 044224 0000 0400 ALL 1 - 1C 001462 044251 7777 7377 ALL 1 - 2C 001462 044345 7777 7377 ALL 1 - 2C 001462 044356 7777 7357 ALL 1 - 2C 001462 050744 0000 0440 ALL 1 - 1C 001462 060073 7777 7337 ALL 1 - 2C 001462 060074 0000 0440 ALL 1 - 1C 001462 060074 7777 7337 ALL 1 - 2C 001462 060120 0000 0400 ALL 1 - 1C 001462 061341 0000 0440 ALL 1 - 1C 001462 061343 7777 7337 ALL 1 - 2C 001462 061345 0000 0400 ALL 1 - 1C 001462 061351 0000 0400 ALL 1 - 1C 001462 062320 7777 7177 ALL 1 - 2C 001462 062661 0000 0400 ALL 1 - 1C 001462 062764 0000 0600 ALL 1 - 1C 001462 063420 7777 3377 ALL 1 - 2C 001462 063544 7777 3377 ALL 1 - 2C 001462 063644 7777 3377 ALL 1 - 2C 001462 063700 0000 4400 ALL 1 - 1C 001462 063704 0000 4400 ALL 1 - 1C 001462 063704 7777 3377 ALL 1 - 2C 001462 064176 7777 7177 ALL 1 - 2C 001462 064323 0000 0600 ALL 1 - 1C 001462 064324 7777 7177 ALL 1 - 2C 001462 064334 7777 7177 ALL 1 - 2C 001462 064523 7777 3377 ALL 1 - 2C 001462 065140 7777 7377 ALL 1 - 2C 001462 065344 0000 0420 ALL 1 - 1C 001462 065420 7777 3377 ALL 1 - 2C 001462 065424 7777 3377 ALL 1 - 2C 001462 065444 0000 4400 ALL 1 - 1C 001462 065504 0000 4400 ALL 1 - 1C 001462 065550 0000 4400 ALL 1 - 1C 001462 065600 0000 4400 ALL 1 - 1C 001462 065644 0000 4400 ALL 1 - 1C 001462 066007 7777 7377 ALL 1 - 2C 001462 066115 7777 7357 ALL 1 - 2C 001462 066214 7777 7377 ALL 1 - 2C 001462 066311 7777 7377 ALL 1 - 2C 001462 066322 0000 4000 ALL 1 - 1C 001462 066347 7777 7357 ALL 1 - 2C^C .
Testing various Altera software packages for compatibilty with LP6
First I tried :Quartus II 4.2″ on Vectra VE PII-333 under Windows 98. It installed and ran fine. However it does NOT seem to recognise the installed LP6 and MPU. When the “Quartus II 4.2 Programmer” application is run, it only provides the following options:
- ByteBlasterMV or ByteBlaster II
- MasterBlaster
- EthernetBlaster
Next I tried that “Max+Plus II v10.1” CD. Running setup offered a full installation, which I initially declined because it refused to proceed unless Adobe Acrobat V.4 was installed (which it wasn’t). However, it offered to let me install the Student Edition, and so I did that. That version does support the LP6 programmer, and it passed the self-test (which required the 84-pin PLCC adapter to be removed from the MPU unit). However, the Student Edition is crippled (the Simulator and Timing Analyzer are both disabled) so I don’t recommend this as a long-term solution.