Options for doing the level translation include:<\/p>\n
- \n
- TXB0108<\/li>\n
- SN74LVC245A<\/a><\/li>\n
- BSS138<\/a><\/li>\n<\/ul>\n
OMNIBUS Interfacing<\/h4>\n
Steve Lafferty’s webpage on the OMNIBUS 32K RAM board<\/a> has extensive notes regarding the ICs used by DEC.<\/p>\n
Eric Smith’s webpage on DEC bus interface chips<\/a> also has lots of useful information.<\/p>\n
The key points are:<\/p>\n
- \n
- The standard receiver was a “DEC 380” also known as an “SP380”. These are still available on eBay.<\/li>\n
- The standrad Transmitter was a “DEC 8881”. It is an open-collector driver. Output voltage is typically 0.4-0.6 (maximum 0.8V) when sinking 50mA. It is commonly thought that the 8881 is a DEC-rebranded 7439.<\/li>\n<\/ul>\n
In 2014, Vince put together a 32K RAM board based on Steve’s design. Vince’s webpage is here<\/a>, and the PDF of the schematic is here<\/a>.<\/p>\n
The “omniusb” prject uses 7438’s to drive the bus. Its an open-collector 4 x NAND gate, with a maximum output voltage of 0.4V when sinking a 48mA load. The datasheet for the 7438 is here<\/a>.<\/p>\n
A 7406 or 7407 could probably also be used to drive the bus 9they both have open-collector outputs). However, they can only sink 40mAwith an output voltage of 0.7V. The 7406 datasheet is here<\/a>.<\/p>\n
Resources<\/h4>\n
NandLand’s Verilog Totorials and Examples<\/a><\/p>\n
Youtube video: How to create a Quartus Prime project from scratch and assign pins for the DE10-Lite<\/a><\/p>\n
Nandland’s page on tri-state outputs in Verilog<\/a>.<\/p>\n
Verilog on the ATF1508<\/h4>\n
It has been mentioned to me that an old version of Altera’s Quartus II software can be used to develop in Verilog or VHDL to target the Atmel ATF1508AS device.<\/p>\n
The process is documented in Atmel’s Application Note 0916<\/a>.<\/p>\n
The main steps are:<\/p>\n
- \n
- Download and install a version of Quartus II that supported the MAX7000 series (ie version 13.0 SP 1). Make sure you tick the box to download the MAX7000 device support.<\/li>\n
- In Quartus, target the MAX7000 part that has 128 macrocells. I selected EPM7128SLC84-15. Do the pin assignments in Qartus, as if you were intended to use the Altera device.<\/li>\n
- After compiling your design in Quartus, use Atmel’s “pof2jed” Windows utility to convert the .pof file (generated by Quartus) to a .jed file. Note it is important to set JTAG Mode to “On” (rather than “Auto”) and to rick “Enable TDI_PULLUP” and “Enable TMS_PULLUP”, to make sure the JTAG port remains enabled after the programmer operation is completed (so the device can later be re-programmed via the JTAG interface).<\/li>\n
- Program the JEDEC file into the ATF1508AS via a JTAG programmer. Note that you won’t be able to use the Quartus II Programmer software (in comination with a USB Blaster) for this task. The Quartus II Programmer will see the Atmel ATF1508AS in the JTAG chain, but won’t allow a .JED file to be downloaded to it. Instead, you need to use the Atmel ATMISP7 programmer application (in Windows) in combination with the Atmel xxxx1150 JTAG programmer.<\/li>\n<\/ul>\n
Some additional information about the Atmel JTAG interface (and a screenshot showing the pof2jed application) is included in Atmel’s ATF15xx In-System Programming User Guide<\/a>.<\/p>\n
Further information about Atmel’s ATMISP software is available here -> http:\/\/www.microchip.com\/design-centers\/programmable-logic\/spld-cpld\/tools\/software\/atmisp<\/a>.<\/p>\n
Note there is also some more information about the JTAG interface (including recommended pull-up and pull-down resistors) in Altera’s Application Note 95<\/a>.<\/p>\n
Setting up a new project in Quartus Prime 17.1<\/h4>\n
Here are the key steps:<\/p>\n
- \n
- Using Windows Explorer, create a new directory somewhere to hold your project files.<\/li>\n
- From within Quartus, select File -> New Project Wizard<\/li>\n
- At the “Directory, Name, Top-Level Entity” screen: Select the directory that you just created, and give the project a name. Do not use a hyphen in the project name.<\/li>\n
- On the next screen, select “Empty project” (rather than Project template).<\/li>\n
- On the next screen (“Add Files”), just click “Next”<\/li>\n
- On the next screen (“Family, Device & Board Settings”), select this device -> 10M50DAF484C6GES<\/li>\n
- On the next screen (“EDA Tool Settings”), for “Simulation” select “ModelSim-Altera”<\/li>\n<\/ul>\n
You should now be back in the main screen of Quartus. In the “Project Navigator” panel in the top-left corner, you should see a line listing your device, and a line below it with the name of your top-level file (which doesn’t yet exist).<\/p>\n
Click on the left-most icon on the toolbar (“New”). In the listbox that appears, select “Verilog HDL File” and click OK. Your new blank file appears in the editor window. Click on the “Save” icon on the toolbar.<\/p>\n
Type in your Verilog file, and save it.<\/p>\n
The next task is to map your Verilog I\/O signals to the pins on the FPGA.<\/p>\n
Select Assignments -> Pin Planner<\/p>\n
input i_clock;
\n input i_enable;
\n input i_switch_1;
\n input i_switch_2;
\n output o_led_drive;<\/p>\nEP2C5 Cyclone II Mini Board<\/h4>\n
![\"\"](\"https:\/\/i0.wp.com\/avitech.com.au\/wp-content\/uploads\/2018\/05\/EP2C5T144-mini-dev-board.jpg?resize=300%2C200&ssl=1\")
<\/a><\/p>\nThis is a cheap FPGA development board that can be found (in April 2018) on eBay for around A$20.<\/p>\n
It comes with no documentation. You can download the schematic and PCB layout from here<\/a>.<\/p>\n
A simple “Getting Started” guide is available here -> http:\/\/www.leonheller.com\/FPGA\/FPGA.html<\/a><\/p>\n
The next 3 paragraphs largely come from Leon Heller’s web-page. So please look there for a fuller description.<\/p>\n
This board is fitted with an Altera EP2C5T144C8 Cyclone II FPGA. It has 4068 logic elements, 26 x 4k RAM blocks giving a total of 119,898 bits, 13 multipliers, two PLLs, and 89 I\/Os. Maximum clock frequency is 300 MHz.<\/p>\n
Designs are developed for this board using Quartus II 11.0 Web Edition software from the Altera web site.<\/p>\n
The board is fitted with a EPCS4 flash configuration memory chip, and a 50 MHz oscillator. Most of the I\/Os are brought out to four 2×14 way headers, which may be connected to external circuitry via wire jumpers, or PCBs fitted with matching sockets. Three LEDs are connected to pins 3, 7 and 9, and a push-button is connected to pin 144.<\/p>\n
My stock of MAX7000 CPLDs<\/h4>\n
To be programmable over JTAG, the device needs to be the “s” version (eg EPM7128S).<\/p>\n
Here’s the list of MAX7000’s that I’ve acquired to date:<\/p>\n
- \n
- 5 x EPM7128SLC84-15 purchased on eBay from China on 11\/04\/2018. Total price US$6.40 for the lot, including postage. They arrived “JTAG locked”. I shipped them to Bruce in the U.S. and he unlocked them (on a Data I\/O 2900?). He kept 3 and returned 2 to me. I’m using 2 of these currently (7\/2024), one in the Omnibus high-speed serial board, and the other in the Omnibus 32K\/bootloader board.<\/li>\n
- 4 x EPN7128SLC84-15’s were purchased for US$3.05 each (plus small postage cost) from utsource on 15\/05\/2018 (along with 2 x ATF1508’s). As of 07\/2024, I’m not sure what happened to these.<\/li>\n
- 20 x EPM7128SLC84-15. Purchased on eBay for US$25.60 (for QTY 20) plus US$2.56 postage on 15\/03\/2020. Order quantity was 20, but 25 were delivered. They looked to be new (were still in individual plastic carriers). I tested one of them in July 2024 and it programmed just fine over JTAG interface.<\/li>\n
- 5 x EPM7128SLC84-15N purchased on Aliexpress for A$25.12 on 09\/07\/2024. These all turned out to be OK, but were difficult to program initially. I suspect they had significant oxidisation on the leads. They were JTAG locked, but with perserverance I was about to unlock them on the Altera LP6. The LP6 kept reporting “pin continuity” errors (and so wouldn’t start a programming cycle), but with multiple attempts at cleaning and sanding the legs, each eventually was able to be programmed (and hence JTAG unlocked) on the LP6. Subsequently, each was able to be JTAG programmed using the Altera USB Blaster. However, again, this took several attempts.<\/li>\n<\/ul>\n
Example of EPM7128s on Aliexpress (August 2025):<\/h4>\n
- \n
- Demo Board FPGA Altera CPLD MAX EPM7064 Development Board for AU$29<\/a><\/li>\n
- 10 pieces of EPM7128SLC84 for AU$27.79<\/a><\/li>\n
- 10 pieces of EPM7128SLC84-15N for AU$29.59<\/a><\/li>\n<\/ul>\n
Quartus II for MAX7000 Series<\/h4>\n
The current version of Quartus as at May 2018 (Quartus Prime 17.1) does not support the old MAX7000 series, such as the EPM7128SLC84-15.<\/p>\n
So I downloaded and installed “Quartus II Web Edition” version 13.0sp1. You can choose between 3 download options: Combined Files, Individual Files or DVD Files. I chose the “Individual Files” option, but later came back and downloaded the “DVD FIles”.<\/p>\n
To download the Quartus II software you must be logged into your “myAltera” account. Otherwise you will be presented with a “Sign In” screen when you try to commence the download.<\/p>\n
You will be given a choice between two Download Methods: “Akamai DLM3 Download Manager” or “Direct Download”. If you choose the former, you will be prompted to download and install the Akamai download software, before the download of Altera software proceeds.<\/p>\n
Before commencing the “Individual Files” download operation, I selected the following components:<\/p>\n
- \n
- Quartus II Software<\/li>\n
- ModelSim-Altera Starter Edition<\/li>\n
- Arria II<\/li>\n
- Cyclone II\/III\/IV<\/li>\n
- Cyclone V<\/li>\n
- MAX II, MAX IV, MAX 3000, MAX 7000<\/li>\n
- Quartus II Programmer and SignalTap II<\/li>\n
- Quartus II Help<\/li>\n<\/ul>\n
This resulted in a download of 4.07GB.<\/p>\n
During the installation process, it reported that the required disk space was 10622MB.<\/p>\n
This software installed fine on Windows 10 on my Surface Pro 4. However, the Quartus II Programmer was unable to see any devices on the JTAG chain (though the application could see the USB Blaster), and it caused Windows to crash every 10 minutes or so.<\/p>\n
This problem is documented by Altera on this web page<\/a>. I downloaded the updated USB Blaster drivers that are mentioned on that page. They are available from here -> https:\/\/www.altera.com\/content\/dam\/altera-www\/global\/en_US\/kdb\/rd05162012_935\/usb-blaster.zip<\/a>.<\/p>\n
I deleted the old drivers without any trouble. But when I tried to install the “new” (November 2011) drivers, Windows 10 reported a “bad hash” (or similar message) and refused to install them. It turns out this is because the drivers are unsigned. You need to go through a special shutdown\/restart process to allow the unsigned drivers to be loaded. The process is shown on this Youtube video<\/a>. After following that process, I installed the new drivers successfully. The Quartus II Programmer was now able to see the JTAG chain, and the computer-crashing problem ceased.<\/p>\n
Update July 2024<\/strong><\/p>\n
I decided to install Quartus II 13.0 SP1 on a Pentium 3 machine (my Super P3-500 tower). Basic specs of that machine are:<\/p>\n
- \n
- Pentium III, 500 Mhz<\/li>\n
- Motherboard: XXX<\/li>\n
- 32GB DOM SSD IDE hard drive<\/li>\n
- 384MB PC100 168-pin SDRAM<\/li>\n
- 2 x USB 1.0 ports<\/li>\n
- Video card:<\/li>\n<\/ul>\n
I first installed Windows XP SP3 using the VL (Volume Licensing) software and CDKEY downloaded from archive.org. This version appears not to need to “phone home” to Microsoft to validate the CDKEY (whereas the SP2 VL does need to do that validation within the first 30 days).<\/p>\n
I then installed Quartus II 13.0 SP1, the Help files, and MAXII family devices (Files “QuartusSetupWeb-13.0.1.232.exe”, “QuartusHelpSetup-13.0.1.232.exe” and “max_web-13.0.1.232.qdz”). By having these 3 files in the same temporary directory (or on a USB stick), Quartus II will give you the option to install the main software, the help files, and the devices at the same time. The install of Quartus II went smoothly (but took approximately 2.5 hours from a USB stick on a USB 1.0 port), but it would not run. It reports the following error: “The application failed to initialize properly (0xc0150002). Click on OK to terminate the application”. It turns out this is because the “Microsoft Visual C++ Redistributable” has not been installed. I found and installed the 2005 version of the redistributable. It installed fine, but the error persisted. So I deleted that and installed the 2008 redistributable (filename is “vcredist_x86 (2008).exe”. Finally, success! Quartus II 13.0 SP1 now runs fine on the PIII-500 machine.<\/p>\n
I then investigated what programmers are supported by this setup. ByteBlaster (parallel port cable) is supported without any need for special drivers. USB Blaster is supported, but you first need to install [this driver] through Device Manager. And unfortunately the Altera LP6 ISA card is not found or supported by this version of Quartus II (even if it is plugged into the ISA slot).<\/p>\n
Miscellaneous Resources<\/h4>\n
Youtube Video by Greg Crist: Getting started with Verilog Testbenches<\/a><\/p>\n
Setting up Simulation in Quartus II<\/h4>\n
There are several ways this can be done.<\/p>\n
For example, you can write code in Quartus II that will define the output timespan and resolution, and provide the simulation inputs.<\/p>\n
I prefer the ‘Univeristy Program VWF” graphical approach. This involves using File -> New to create a graphical display of inputs and outputs, and using Edit -> Value -> Overwrite Clock to stimulate the inputs. This technique is described in this YouTube video -> Creating a Waveform Simulation for Altera FPGAs (Quartus version 13 and newer) (Sec 4-4B )<\/a><\/p>\n
- 10 pieces of EPM7128SLC84 for AU$27.79<\/a><\/li>\n
- Demo Board FPGA Altera CPLD MAX EPM7064 Development Board for AU$29<\/a><\/li>\n
- BSS138<\/a><\/li>\n<\/ul>\n