SD Systems SBC-200 S-100 Board

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Where did this come from?

This board is part of an SD Systems 600 computer that I am attempting to restore. The 600 (which I will write about in more detail on a separate page) is an “all in one” S-100 system that includes an S-100 backplane, various S-100 boards (all designed by SD Systems), power supply, 8″ floppy drive, 5.25″ MFM hard drive, 12″ monochrome monitor and full keyboard.

The power supply and monitor are now working, but there are no signs of life for the system overall. So I decided to remove the SBC-200 CPU board and get that working on the bench first. Then I will put it back into the S-100 backplane and use it to test and diagnose the other S-100 boards.

SBC-200 as received

My SBC-200 had a rather large daughter board plugged into the Z-80 socket. This board then connected to an MFM Hard Drive interface via a 26-way data cable. The bottom of this PCB is marked “Blue Sky” and “Z-80 – Konan Interface”. I decided to remove this daughter board for the time being, as it obscures about 20% of the S-100 board area. There was a single length of wire wrap wire connecting Pin 5 of U29 on the SBC-200 to Pin 2 of the 74LS32 on the daughter board. I unsoldered that wire and removed the daughter board.

The SBC-200 (when I received the 600) had only one ROM installed: an unlabelled 2716 in location ROM2. That location covers memory address range F000-F7FF, and the SBC-200 was configured to boot at address 0xF000. I haven’t yet explored that ROM, but I assume it contains a bootloader for the MFM hard drive that interfaces to the SBC-200 via the daughter board mentioned above.

I then went looking for a Monitor ROM for this machine. On Herb Johnson’s website, I found a collection of ROM files for the SBC-200, in both assembler and hex formats. There seems to be two versions of the Monitor that use the VDB8024 board as the system console (SDMONV21 and SDMONV3), and one version that uses the SBC-200’s serial port as the system console (MSMONR21). The VDB8024 is an S-100 board by SD Systems that provides input via a parallel keyboard and output on to a monochrome monitor that plugs directly into the VDB8024.

I decided to start with MSMONR21.Z80, as I wanted to try to bring up the SBC-200 on a stand-alone basis (without the need for any other S-100 cards) using the SBC-200’s serial port as the system console. I figured this should be possible, as the SBC-200 has 1K of static RAM on board. The configuration changes that I made to the SBC-200 were:

  • Assembled MSMONR21.Z80 using George Phillips’ ZASM assembler on a Windows 8 machine
  • FTP’d the assembled Intel Hex file to my MSDOS machine that has my Needham’s Electronics EMP-10 EPROM Programmer attached to it
  • Burn MSMONR21.HEX to a 2716 EPROM using the EMP-10
  • Install the new EPROM in ROM0 slot (U36). I left the existing ROM in the ROM2 slot
  • U36 must be configured for address 0xE000
  • In the “ROM Select” jumper block, originally there was only one jumper installed. This jumper was in the second-to-bottom location and was needed to enable ROM2. I now installed two further jumpers. The first goes at the fourth-to-bottom location to enable ROM0. The other goes in the bottom location to enable the1K of onboard RAM (this was previously omitted because the system apparently relied instead on the 64K of dynamic RAM on the Expandoram II board)
  • Moved Jumper X18 from the 1-2 position (upper) which had been required to boot at address 0xF000), to the 2-3 position (lower) so the SBC-200 will boot at address 0xE000
  • Moved Jumper X13 from the 2-3 position (lower) which routes the incoming DSR signal to the 8251A’s /DSR pin, to the 1-2 position (upper) so the RXD line instead gets routed to the 8251’s /DSR input. Note: I didn’t do this initially, but it is required (otherwise the SBC-200 will hang indefinitely when it is booted). See the discussion that follows in relation to this issue.

After doing these steps (except the last one – which I didn’t realise was necessary at the time), I wired up the SBC-200 as a single-board system on my workbench (see photo on the right), with a VT220 terminal attached to the SBC-200’s serial port. To bring up the monitor’s dot prompt, you are supposed to hit CR on the terminal, so that the SBC-200 can detect the baud rate (which must be in the range 110 to 9600 baud), and the Monitor will then issue the dot prompt and wait for you to enter a monitor command.

Sadly I was disappointed to find that my SBC-200 was non-responsive. I did the usual initial checks (power supply voltages, system clock, signals at the 8251A USART’s TxD and RxD pins, Z-80 reset signal, CS pins on the EPROMs and 2114 RAMs, etc).

The first anomaly that I found is that the SBC-200 doesn’t generate a valid /RESET signal on power-up. XXX has reported a similar problem with his SBC-200 and fixed it by changing XXX. I found that by pressing a RESET switch connected to Pin XXX of the S-100 connector, my SBC-200 does reset correctly, so I just have to remember to press the RESET switch after I power up each time. Not a big problem.

The second anomaly that I found was that the 8251A was not functioning as I expected. There were no incoming baud rate clock signals on /TxC (Pin 9) or /RxC (Pin 25), and RxRDY (Pin 14) does not come high when CR is hit on the terminal. I now know these were false leads – but this wasn’t obvious to me at the time. The reason why there was no /TxC or /RxC signals is because during the baud rate negotiation process the Z-80 CTC is outputting a 2.0 MHz signal and this is effectively blocked by the 74LS122 re-triggerable one-shot (U15). I guessed that RxRDY (which should come high once a full byte has been received by the 8251A) won’t come high in this condition, as there is no /RxC.

So at this point I set about writing some small test programs (TEST01, TEST02, TEST03) which I burned to EPROM and tested one-by-one in the ROM0 slot of the SBC-200. None of these programs require any RAM. They are intended to test just a very minimal system. TEST01 just executes a NOP repeatedly. TEST02 configures the CTC and USART, then outputs an ASCII ‘0’ repeatedly at 9600 baud. TEST03 outputs the entire upper-case alphabet once per reset.

Here are the test programs in Assembler, Listing and Intel Hex formats:

Assembly Language Listing File Intel Hex
test01.asm test01.lst test01.hex
test02.asm test02.lst test02.hex
test03.asm test03.lst test03.hex

In the process of getting these test to run successfully (and examining lots of signals with my 2-channel DSO) I learned a lot about the CTC and USART. I then went back and installed the MSMONR21 EPROM in the ROM0 slot. Pressing CR on the Terminal still doesn’t seem to be doing anything. There is no output being sent to the Terminal.

I decided to take a closer look at the Monitor source code, to see where and why the Monitor is non-responsive. Here are the first 24 lines of the Monitor source code:

  72:    0+10	E000  C30FE0  	START:	JP	MCOLD
  73:   10+10	E003  C379E0  	MONITR: JP	MENTRY
  74:   20+10	E006  C30FE7  	CSE:	JP	MCONST
  75:   30+10	E009  C317E7  	CIE:	JP	MCONIN
  76:   40+10	E00C  C325E7  	COE:	JP	MCONOT
  77:				
  78:   50+11	E00F  DB7F    	MCOLD:	IN	A,(7FH)
  79:   61+10	E011  2160FF  		LD	HL,SBUFF
  80:   71+16	E014  22E6FF  		LD	(BRKSP),HL
  81:   87+4	E017  AF      		XOR	A
  82:   91+13	E018  32C0FF  		LD	(STKTOP),A
  83:  104+7	E01B  3E4E    		LD	A,4EH
  84:  111+11	E01D  D37D    		OUT	(CSTAT),A
  85:  122+7	E01F  3E37    		LD	A,37H
  86:  129+11	E021  D37D    		OUT	(CSTAT),A
  87:  140+7	E023  3E45    		LD	A,45H
  88:  147+11	E025  D378    		OUT	(78H),A
  89:  158+7	E027  0E7D    		LD	C,7DH		;difference in timing for
  90:  165+10	E029  110100  		LD	DE,0001H	;load of port
  91:  175+12	E02C  ED78    	WAIT0:	IN	A,(C)		;plus a ready wait on bit 7
  92:  187+10	E02E  F22CE0  		JP	P,WAIT0
  93:  197+6	E031  13      	WAIT1:	INC	DE
  94:  203+12	E032  ED78    		IN	A,(C)
  95:  215+10	E034  FA31E0  		JP	M,WAIT1

By looking at the the CS line on the 2114 RAMs, I could see that only 3 accesses to RAM were occurring before the Monitor entered some kind on endless loop. These correspond to the two memory writes in Line 78, and the one memory write in Line 82. Because no further memory access is occurring, it is reasonable to assume the code is looping endlessly in one of the two loops at Lines 91 to 95.

The first loop waits for the start of a start bit from the terminal, and the second loop then counts the duration of the start bit. This count (in DE) is then used in the next code fragment (not shown here) that calculates the baud rate generator parameters for the CTC and USART, and then configures the CTC and USART appropriately.

I can see that the loop at Lines 91-92 waits until Bit 7 of Port 0x7D is set to 1. Port 0x7D is the 8251A’s status port. Looking at the datasheet for the 8251A, Figure 13 tells us that this bit is set when the 8251A’s /DSR input pin is low (ie active).

So this raised a new question for me: Why is the Monitor looking at the /DSR line when it is trying to detect the duration of the start bit? Looking at the Schematic for the SBC-200, things became clearer. Jumper X11 is a 3-pin header that allows the /DSR input to the 8251A to be connected either to the DTR signal from the RS232 connector (Edge Connector J2 Pin 14, via U2 Pins 10 & 9) if Pins 2-3 are connected, or to the RxD signal (Pin 3) on the 8251A if pins 1-2 are connected. So I take a look at the SBC-200 and find that the jumper is indeed in the 2-3 position. I move the X11 jumper to the 1-2 position, and now when I hit CR on the terminal and Monitor sends the dot prompt to the terminal as expected.

An initial play with the monitor commands show that the SBC-200 and the Monitor now seem to be working normally.

So the lessons learned here are:

  • My SBC-200 did not have any faults (other than perhaps the RESET issue mentioned above)
  • The MSMONR21 Monitor (which uses the SBC-200’s serial port) on Herb Johnson’s website works fine
  • MSMONR21 will NOT work unless the DSR jumper (X11) is in the 1-2 position

Firmware

As mentioned above, I am using MSMONR21 as the Monitor ROM in slot ROM0 at address 0xE000.

I have temporarily removed the original EPROM from slot ROM2 (this is the EPROM that I suspect is used to boot the 5MB MFM hard drive). In its place I am now using DDBIOS42, downloaded from Herb Johnson’s website. I couldn’t successfully load that file into the EPROM programmer, as it reported a checksum error. So instead I loaded it into Hex Editor Neo on my PC, and then generated the binary file (DDBIOS42.BIN) from there.

With this combination of ROMs installed, all Monitor commands that I’ve tested so far appear to be working. For example, If I issue the command “Z 00″ the 8” floppy drive steps through a format sequence. The “W” command (to write memory to disk) appears to work, and very promptly returns to the dot prompt. But the “R” command usually hangs. My next task here is to remove the floppy drive, clean it, and test it on my disk imaging station.

Monitor commands

[TO DO]

Building a CP/M BIOS for the SBC-200 and Versafloppy II

It seems the DDBIOS supplied by SD Systems is only good for booting SD Systems’ own version of CP/M called “SDOS”. My understanding is that if you want to boot and use a generic version of CP/M, you will need to replace DDBIOS. It appears that John Monahan did this back in around 1981, and wrote up and published the instructions and files necessary to do so.

Although I haven’t yet completed this task, it is definitely on my to-do list.

These files appear to have been re-published in the Walnut Creek CP/M CD-ROM (November 1994). The files from the CDROM appear to be re-published at present on various sites. If you search for “/SIMTEL/SIGM/VOLS000/VOL026” you should get a directory listing the files you need (and many other files that you don’t need).

Start with the file MYDDBIOS.DOC. This file describes the process of generating the CP/M boot disk, and lists the other files that you need to download.

The other files that you need to download for this process are:

Documentation

Useful links